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INTEGRATED CIRCUITS
PCA9557 8-bit I2C and SMBus I/0 port with reset
Product data File under Integrated Circuits -- ICL03 2001 Dec 12
Philips Semiconductors
Philips Semiconductors
Product data
8-bit I2C and SMBus I/0 port with reset
PCA9557
The system master can also invert the PCA9557 inputs by writing to the active HIGH polarity inversion register. Finally, the system master can reset the PCA9557 in the event of a timeout by asserting a LOW in the reset input. The power-on reset puts the registers in their default state and initializes the I2C/SMBus state machine. The RESET pin causes the same reset/initialization to occur without depowering the part.
FEATURES
PCA9556
PIN CONFIGURATION
SCL 1 SDA 2 16 VDD 15 RESET 14 I/O7 13 I/O6 12 I/O5 11 I/O4 10 I/O3 9 I/O2
* Lower voltage, higher performance migration path for the * 8 general purpose input/output expander/collector * Input/output configuration register * Active HIGH polarity inversion register * I2C and SMBus interface logic * Internal power-on reset * Noise filter on SCL/SDA inputs * Active LOW reset input * 3 address pins allowing up to 8 devices on the I2C/SMBus * High impedance open drain on I/O0 * No glitch on power-up * Power-up with all channels configured as inputs * Low standby current * Operating power supply voltage range of 2.3 V to 5.5 V * 5 V tolerant inputs/outputs * 0 to 400 kHz clock frequency * ESD protection exceeds 2000 V HBM per JESD22-A114, * Latch-up testing is done to JESDEC Standard JESD78 which * Package offer: SO 16, TSSOP 16
DESCRIPTION
The PCA9557 is a silicon CMOS circuit which provides parallel input/output expansion for SMBus and I2C applications. The PCA9557 consists of an 8-bit input port register, 8-bit output port register, and an I2C/SMBus interface. It has low current consumption and a high impedance open drain output pin, I/O0. The system master can enable the PCA9557's I/O as either input or output by writing to the configuration register. exceeds 100 mA 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
A0 3 A1 4 A2 5 I/O0 6 I/O1 7 VSS 8
su01045
Figure 1. Pin configuration
PIN DESCRIPTION
PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SYMBOL SCL SDA A0 A1 A2 I/O0 I/O1 VSS I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 RESET VDD FUNCTION Serial clock line Serial data line Address input 0 Address input 1 Address input 2 I/O0 (open drain) I/O1 Supply ground I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Active low reset input Supply voltage
ORDERING INFORMATION
PACKAGES 16-Pin Plastic SO (narrow) TEMPERATURE RANGE -40 to +85 C ORDER CODE PCA9557D DRAWING NUMBER SOT109-1 SOT403-1
16-Pin Plastic TSSOP -40 to +85 C PCA9557PW Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging. SMBus as specified by the Smart Battery System Implementers Forum is a derivative of the Philips I2C patent. I2C is a trademark of Philips Semiconductors Corporation.
2001 Dec 12
2
853-2308 27449
Philips Semiconductors
Product data
8-bit I2C and SMBus I/0 port with reset
PCA9557
BLOCK DIAGRAM
PCA9557
A0 A1 A2 SCL SDA INPUT FILTER I2C/SMBus CONTROL 8-BIT INPUT/ OUTPUT PORTS I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
WRITE pulse READ pulse VDD VSS POWER-ON RESET
RESET
SW00827
Figure 2. Block diagram
SYSTEM DIAGRAM
Input Port Q7 Polarity Inversion Q7 Configuration Q7 Output Port 1.1 K Q7 I/O0 6
VCC= 16 GND = 8
Q6 1.1 K 15 RESET Q5
Q6
Q6
Q6
I/O1
7
Q5
Q5
Q5
I/O2
9
1.6 K 1 SCL
I2C/SMBus Interface logic
Q4
Q4
Q4
Q4
I/O3
10
1.6 K 2 SDA
Q3
Q3
Q3
Q3
I/O4
11
5
A2
or
1.1 K
Q2
Q2
Q2
Q2
I/O5
12
4
A1
or
1.1 K
Q1
Q1
Q1
Q1
I/O6
13
3
A0
or
1.1 K
Q0
Q0
Q0
Q0
I/O7
14
SW00794
Figure 3. System diagram
2001 Dec 12
3
Philips Semiconductors
Product data
8-bit I2C and SMBus I/0 port with reset
PCA9557
SIMPLIFIED SCHEMATIC OF I/O0
DATA FROM SHIFT REGISTER CONFIGURATION REGISTER DATA FROM SHIFT REGISTER WRITE CONFIGURATION PULSE WRITE PULSE D FF CK Q D FF I/O0 CK Q ESD PROTECTION DIODE Q Q OUTPUT PORT REGISTER DATA
OUTPUT PORT REGISTER INPUT PORT REGISTER D FF READ PULSE CK Q Q
VSS
INPUT PORT REGISTER DATA
DATA FROM SHIFT REGISTER WRITE POLARITY PULSE
D FF CK
Q
POLARITY REGISTER DATA
Q
POLARITY INVERSION REGISTER
SW00795
NOTE: On power-up or reset, all registers return to default values. Figure 4. Simplified schematic of I/O0
2001 Dec 12
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Philips Semiconductors
Product data
8-bit I2C and SMBus I/0 port with reset
PCA9557
SIMPLIFIED SCHEMATIC OF I/O1 TO I/O7
DATA FROM SHIFT REGISTER CONFIGURATION REGISTER DATA FROM SHIFT REGISTER D FF WRITE CONFIGURATION PULSE WRITE PULSE CK Q D FF I/O1 TO I/O7 CK Q ESD PROTECTION DIODE Q Q ESD PROTECTION DIODE OUTPUT PORT REGISTER DATA VDD
OUTPUT PORT REGISTER INPUT PORT REGISTER D FF READ PULSE CK Q Q
VSS
INPUT PORT REGISTER DATA
DATA FROM SHIFT REGISTER WRITE POLARITY PULSE
D FF CK
Q
POLARITY REGISTER DATA
Q
POLARITY INVERSION REGISTER
SW00796
NOTE: On power-up or reset, all registers return to default values. Figure 5. Simplified schematic of I/O1 to I/O7
2001 Dec 12
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Philips Semiconductors
Product data
8-bit I2C and SMBus I/0 port with reset
PCA9557
DEVICE ADDRESS
Following a START condition the bus master must output the address of the slave it is accessing. The address of the PCA9557 is shown in Figure 6. To conserve power, no internal pullup resistors are incorporated on the hardware selectable address pins and they must be pulled HIGH or LOW.
Register 1 - Output Port Register
bit
default
O7 0
O6 0
O5 0
O4 0
O3 0
O2 0
O1 0
O0 0
slave address
This register reflects the outgoing logic levels of the pins defined as outputs by the Configuration Register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, NOT the actual pin value.
0
0
1
1
A2
A1
A0 R/W
Register 2 - Polarity Inversion Register
bit N7 1 N6 1 N5 1 N4 1 N3 0 N2 0 N1 0 N0 0
default
fixed
programmable
su01048
Figure 6. PCA9557 address The last bit of the slave address defines the operation to be performed. When set to logic 1 a read is selected while a logic 0 selects a write operation.
This register enables polarity inversion of pins defined as inputs by the Configuration Register. If a bit in this register is set (written with `1'), the corresponding port pin's polarity is inverted. If a bit in this register is cleared (written with a `0'), the corresponding port pin's original polarity is retained.
CONTROL REGISTER
Following the successful acknowledgement of the slave address, the bus master will send a byte to the PCA9557, which will be stored in the control register. This register can be written and read via the I2C bus.
Register 3 - Configuration Register
bit
default
C7 1
C6 1
C5 1
C4 1
C3 1
C2 1
C1 1
C0 1
0
0
0
0
0
0
D1
D0
This register configures the directions of the I/O pins. If a bit in this register is set, the corresponding port pin is enabled as an input with high impedance output driver. If a bit in this register is cleared, the corresponding port pin is enabled as an output.
SW00953
POWER-ON RESET
When power is applied to VDD, an internal power-on reset holds the PCA9557 in a reset state until VDD has reached VPOR. At that point, the reset condition is released and the PCA9557 registers and I2C/SMBus state machine will initialize to their default states. For a power reset cycle, VDD must be set to 0 V, then ramped back to the operating voltage.
Figure 7. Control Register
REGISTER DEFINITION
D1 0 0 1 1 D0 0 1 0 1 NAME Register 0 Register 1 Register 2 Register 3 TYPE Read Read/Write Read/Write Read/Write FUNCTION Input port register Output port register Polarity inversion register Configuration register
RESET INPUT
A reset can be accomplished by holding the RESET pin LOW for a minimum of tW. The PCA9557 registers and SMBus/I2C state machine will be held in their default state until the RESET input is once again HIGH. This input typically requires a pull-up to VCC.
REGISTER DESCRIPTION Register 0 - Input Port Register
I7 I6 I5 I4 I3 I2 I1 I0 This register is an read-only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration Register. Writes to this register have no effect.
2001 Dec 12
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Philips Semiconductors
Product data
8-bit I2C and SMBus I/0 port with reset
PCA9557
CHARACTERISTICS OF THE I2C-BUS
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P) (see Figure 9).
Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 8).
System configuration
A device generating a message is a `transmitter', a device receiving is the `receiver'. The device that controls the message is the `master' and the devices which are controlled by the master are the `slaves' (see Figure 10).
SDA
SCL data line stable; data valid change of data allowed
SW00363
Figure 8. Bit transfer
SDA
SDA
SCL S START condition P STOP condition
SCL
SW00365
Figure 9. Definition of start and stop conditions
SDA SCL
MASTER TRANSMITTER/ RECEIVER
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
I2C MULTIPLEXER
SLAVE
SW00366
Figure 10. System configuration
2001 Dec 12
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Philips Semiconductors
Product data
8-bit I2C and SMBus I/0 port with reset
PCA9557
Acknowledge
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse, set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START condition 1 2 8 9 clock pulse for acknowledgement
SW00368
Figure 11. Acknowledgement on the
I2C-bus
2001 Dec 12
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Philips Semiconductors
Product data
8-bit I2C and SMBus I/0 port with reset
PCA9557
Bus Transactions
Data is transmitted to the PCA9557 registers using Write Byte transfers (see Figures 12 and 13). Data is read from the PCA9557 registers using Read and Receive Byte transfers (see Figures 14 and 15).
SCL
1
2
3
4
5
6
7
8
9 command byte
slave address
data to port
SDA
S
0
0
1
1
A2
A1
A0
0 R/W
A
0
0
0
0
0
0
0
1
A acknowledge from slave
DATA 1
A
P
start condition
acknowledge from slave
acknowledge from slave
WRITE TO PORT
DATA OUT FROM PORT tpv
DATA 1 VALID
SW00797
Figure 12. WRITE to output port register
SCL
1
2
3
4
5
6
7
8
9
slave address
command byte
data to register
SDA
S
0
0
1
1
A2
A1
A0
0 R/W
A
0
0
0
0
0
0
1
1/0
A acknowledge from slave
DATA
A
P
start condition
acknowledge from slave
acknowledge from slave
SW00798
Figure 13. WRITE to I/O configuration or polarity inversion registers
slave address
acknowledge from slave
acknowledge from slave
slave address
acknowledge from slave
data from register
acknowledge from master
S
0
0
1
1
A2 A1 A0
0 R/W
A
COMMAND BYTE
A
S
0
0
1
1
A2 A1 A0
1 R/W
A
DATA first byte
A
at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter data from register no acknowledge from master
DATA last byte
NA
P
su01052
Figure 14. READ from register
2001 Dec 12
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Philips Semiconductors
Product data
8-bit I2C and SMBus I/0 port with reset
PCA9557
slave address
data from port
data from port
SDA
S
0
0
1
1
A2
A1
A0
1 R/W
A acknowledge from slave
DATA 1
A acknowledge from master
DATA 4
NA
P stop condition
start condition
no acknowledge from master
READ FROM PORT
DATA INTO PORT tph
DATA 2
DATA 3 tps
DATA 4
SW00799
NOTES: 1. This figure assumes the command byte has previously been programmed with 00h. 2. Transfer of data can be stopped at any moment by a stop condition. When this occurs, data present at the last acknowledge phase is valid (output mode). Input data is lost. Figure 15. READ input port register
TYPICAL APPLICATION
VDD 2 k VDD SCL SDA MASTER CONTROLLER RESET 1.6 k 1.6 k 1.1 k 2 k VDD SCL SDA I/01 RESET I/02 GND I/03 PCA9557 I/04 SUBSYSTEM 2 (e.g. counter) RESET INT I/00 SUBSYSTEM 1 (e.g. temp sensor)
I/05 A2
A Controlled Switch (e.g. CBT device) ENABLE
I/06
A1 I/07 A0
B
GND
ALARM SUBSYSTEM 3 (e.g. alarm system)
NOTE: Device address configured as 0011100 for this example I/00, I/01, I/02, configured as outputs I/03, I/04, I/05, configured as inputs I/006, I/07, are not used and have to be configured as outputs
VDD
SW00993
Figure 16. Typical application
2001 Dec 12
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Philips Semiconductors
Product data
8-bit I2C and SMBus I/0 port with reset
PCA9557
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VI II IIHL(max) VI/O VI/O0 II/O0 /O II/O IDD ISS Ptot Tstg Tamb PARAMETER DC supply voltage DC input voltage DC input current Maximum allowed input current through protection diode (I/O1 - I/O7) DC voltage on an I/O as an input other than I/O0 DC voltage on I/O0 as an input DC input current on I/O0 DC output current on an I/O DC supply current DC supply current Total power dissipation Storage temperature range Operating ambient temperature VI VDD or VI VSS CONDITIONS MIN -0.5 VSS - 0.5 -- -- VSS - 0.5 VSS - 0.5 -- -- -- -- -- -- -65 -40 MAX +6 5.5 20 400 5.5 5.5 +400 -20 50 85 100 200 +150 +85 UNIT V V mA A V V A mA mA mA mA mW C C
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC24 under "Handling MOS devices".
2001 Dec 12
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Philips Semiconductors
Product data
8-bit I2C and SMBus I/0 port with reset
PCA9557
DC CHARACTERISTICS
SYMBOL Supplies VDD IDD Istbl Istbh VPOR Supply voltage Supply current Standby current Standby current
VDD = 2.3 to 5.5 V; VSS = 0 V; Tamb = -40 to +85 C; unless otherwise specified. LIMITS PARAMETER CONDITIONS MIN TYP MAX UNIT
2.3 Operating mode; VDD = 3.6 V; no load; VI = VDD or VSS; fSCL = 100 kHz Standby mode; VDD = 5.5 V; no load; VI = VSS; fSCL = 0 kHz; I/O = inputs Standby mode; VDD = 5.5 V; no load; VI = VDD; fSCL = 0 kHz; I/O = inputs No load; Temp = 25 C VI = VDD or VSS -- -- -- --
-- -- -- -- 1.65
5.5 1 1 1 --
V A A A V
Power-on reset voltage
Input SCL; input/output SDA VIL VIH IOL IL CI I/Os VIL VIH IOL IOH LOW level input voltage HIGH level input voltage LOW level output current HIGH level output current except I/O0 HIGH level output current on I/O0 Input leakage current Input capacitance Output capacitance VOL = 0.55 V; note 1 VOH = 2.4 V; note 2 VOH = 4.6 V VOH = 3.3 V VDD = 5.5 V, VI = VSS -0.5 2.0 8 4 -- -- -- -- -- -- -- 10 -- -- -- -- 3.7 3.7 0.8 5.5 -- -- 1 1 -100 5 5 V V mA mA A A pF pF LOW level input voltage HIGH level input voltage LOW level output current Leakage current Input capacitance VOL = 0.4 V VI = VDD or VSS VI = VSS -0.5 0.7 VDD 3 -1 -- -- -- -- -- 6 0.3 VDD 5.5 -- +1 10 V V mA A pF
IL CI CO VIL VIH
Select Inputs A0, A1, A2, and RESET LOW level input voltage HIGH level input voltage -0.5 2.0 -1 -- -- -- 0.8 5.5 1 V V A
ILI Input leakage current NOTES: 1. The total amount sunk by all I/Os must be limited to 100 mA and 25 mA per bit. 2. The total current sourced by all I/Os must be limited to 85 mA and 20 mA per bit.
2001 Dec 12
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Philips Semiconductors
Product data
8-bit I2C and SMBus I/0 port with reset
PCA9557
AC SPECIFICATIONS
SYMBOL fSCL tBUF tHD;STA tSU;STA tSU;STO tHD;DAT tVD;ACK tVD;DAT tSU;DAT tLOW tHIGH tF tR tSP Port Timing tPV tPV tPS tPH Reset tW tREC tRESET Reset pulse width Reset recovery time Time to reset 4 0 400 -- -- -- 4 0 400 -- -- -- ns ns ns Output data valid I/O0 Output data valid I/O1 - I/O7 Input data setup time Input data hold time -- -- 0 200 250 200 -- -- -- -- 0 200 250 200 -- -- ns ns ns ns PARAMETER Operating frequency Bus free time between STOP and START conditions Hold time after (repeated) START condition Repeated START condition setup time Setup time for STOP condition Data in hold time Valid time for ACK Data setup time Clock LOW period Clock HIGH period Clock/Data fall time Clock/Data rise time Pulse width of spikes that must be suppressed by the input filters condition2 Data out valid time3 STANDARD MODE I2C BUS MIN 0 4.7 4.0 4.7 4.0 0 -- -- 250 4.7 4.0 -- -- -- MAX 100 -- -- -- -- -- 1 1 -- -- -- 300 1000 50 FAST MODE I2C BUS MIN 0 1.3 0.6 0.6 0.6 0 -- -- 100 1.3 0.6 20 + 0.1 Cb1 20 + 0.1 Cb --
1
UNITS 400 -- -- -- -- -- 0.9 0.9 -- -- -- 300 300 50 kHz s s s s ns s s ns s s ns ns ns
MAX
NOTES: 1. Cb = total capacitance of one bus line in pF. 2. tVD;ACK = time for Acknowledgement signal from SCL low to SDA (out) low. 3. tVD;DAT = minimum time for SDA data out to be valid following SCL low.
SDA
tBUF
tLOW
tR
tF
tHD;STA
tSP
SCL
tHD;STA P S tHD;DAT tHIGH tSU;DAT Sr
tSU;STA
tSU;STO P
SU00645
Figure 17. Definition of timing on the
I2C-bus
2001 Dec 12
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Philips Semiconductors
Product data
8-bit I2C and SMBus I/0 port with reset
PCA9557
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
2001 Dec 12
14
Philips Semiconductors
Product data
8-bit I2C and SMBus I/0 port with reset
PCA9557
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
2001 Dec 12
15
Philips Semiconductors
Product data
8-bit I2C and SMBus I/0 port with reset
PCA9557
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011.
Data sheet status
Data sheet status [1] Objective data Preliminary data Product status [2] Development Qualification Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Product data
Production
[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2001 All rights reserved. Printed in U.S.A. Date of release: 12-01
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Document order number:
9397 750 09217
Philips Semiconductors
2001 Dec 12 16

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